Comparative Study of I on /I off Ratio of Silicon Nanowire Transistor (SNWT) with Planner MOSFET

Abstract

In this paper, a general approach, that considers both electrostatic integrity and quantum confinement, so called the “EQ approach”, to compare the device performance of nanoscale Si FETs with various gate geometry configurations, i.e., planar MOSFETs versus SNWTs, is proposed. A better gate control, e.g., a better sub threshold swing and a higher ON-OFF current ratio is reported. This approach is based on the use of L_Qvs. L_Eplot, where L_Q is the quantum confinement length, and L_E denotes the electrostatic scale length.